Technical Field
The present invention generally relates to semiconductor processing and devices, and more particularly to flowing interconnects to handle reduced dimensional configurations.
Description of the Related Art
Semiconductor processing is often guided by ever decreasing node sizes. As dimensions shrink, further challenges arise in many processing steps and structures. This includes interconnect structures, which as a result of reduced node size suffers from resistivity issues and formation issues. Interconnects with liner requirements for copper accelerate copper resistivity, which increases due to dimensional restrictions. At small dimensions (e.g., critical dimensions (CD) under 20 nm), interconnect fills with any kind of metal are very challenging. This is further complicated for high melting point metals, which are difficult to process, and their high temperature processing can result in damaging effects to surrounding materials and structures.